Continuing increases in the complexity and density of integrated circuit (IC) components within a circuit chip have imposed an escalating challenge to the testing of such circuitry. By some estimation, the cost of testing can contribute up to 20% to the total cost of manufacturing. To achieve economy of scales, it is critical that the cost of testing be minimized.
Minimizing cost in high-volume manufacturing requires that the testability of the circuitry be considered up front since both time and money are required to achieve a desired level of quality. Various techniques for testing have existed for many years. A technique that has gained widespread acceptance in the testing community is scan-based testing. In detecting faults within the IC components, various forms of scan-based testing are used for maximizing accessibility and observability. Accessibility is the ability to establish specific state data at the desired nodes of the IC components, while observability is the ability to determine specific state data at any node within the IC components.
The terms “state” and “state data” will be used interchangeably and are each defined as a symbol or representation of encoded information utilized for data processing, and may be represented by a waveform.
In scan-based testing, an input test sequence of scan-in states (i.e., input stimulus of logic 0 or logic 1) are serially shifted into a scan chain of a device under test (DUT). A number of test executions are performed on the DUT during successive tester cycles to produce in the scan chain an output test sequence of scan-out states (i.e., output responses of logic 0 or logic 1). The output test sequence is subsequently shifted out of the scan chain and compared with a known sequence of expected states (i.e., expected responses of logic 0, logic 1, don't care, or high-impedance) for determining possible faults within the DUT. For a typical DUT having a large array of IC components, a lengthy scan data sequence is needed to test the embedded combinational logics of the IC components.
While conventional scan-based testing provides a high degree of accessibility and observability, a concern with utilizing a lengthy scan data sequence is that the quantity of scan state data can easily exceed the number of available tester memory locations within the IC tester. A means for resolving the problem of limited availability of tester memory locations is to use multiple scan chains during testing, rather than one lengthy scan chain. One of the drawbacks with this approach is that additional hardware (e.g., scan-in and scan-out pins) is needed to serially shift the multiple scan-chain state data into positions for testing and to serially shift the scan-chain state data out from the DUT for comparing. Such a modification adds to the cost of fabrication. Another concern with utilizing a lengthy scan chain is that the time required to test all the IC components within the DUT can be time-consuming, if each state of scan-in data is entered and each state of scan-out data is compared at the slower of the operation speed of the device (i.e., the device cycle rate) and the operation speed of the tester (i.e., the tester cycle rate). Currently, the continuous increases in the device cycle rate of circuit chips outpace the increases in tester cycle rate that can be achieved by tester upgrades or tester replacement. Thus, the tester cycle rate dictates the speed of the testing operation.
What is needed is a testing method for evaluating IC components within a DUT that is both cost-productive and time-efficient.